Many circuits and systems include circuitry operating in different clock domains. For example, processor circuits often operate at high clock speeds, whereas peripheral circuits run at much lower clock speeds. It is often desirable for circuits of different clock domains to exchange data. For instance, a high clock speed central processor unit (CPU) may write to a data or control register used by a low clock speed peripheral device to control operation of the peripheral. Such a CPU may also read data stored in a register of the low clock speed circuit. However, transferring data between circuits of different clock domains presents problems, particularly where the high and low clock speeds are very different. In one example, peripheral circuits operating at very slow frequencies (e.g., 10-100 KHz) may need to be serviced by a CPU operating at high clock frequencies of 1-100 MHz or even higher. Application software executed by the CPU may need to update or write a value in a peripheral circuit register frequently, such as software running on a high speed processor operating a low clock speed pulse width modulation (PWM) control circuit to control an output signal or actuator. In this example, the processor may implement a closed loop control algorithm by frequently changing a pulse width value controlled by the peripheral. Frequent updates by data writes to the low speed circuit register can cause the CPU to have to wait for a potentially large number of high speed clock cycles to allow a previous data write operation to be synchronized to the low speed clock domain before again updating the peripheral. In some cases more than a thousand CPU cycles elapse just to ensure correct data synchronization. Handshaking schemes using a request-acknowledge peripheral write synchronization protocol may lead to significant data latency for back-to-back updates from fast to slow clock domains, which can inhibit the ability to perform high bandwidth closed loop control using a programmed processor and a low speed peripheral.
Problems may also arise in reading data from a low clock speed peripheral. Reading from a peripheral register poses the possibility of metastability in the data read from a low clock speed domain register. The CPU can perform multiple reads, e.g., three reads, with the CPU comparing the read results and selecting the data if consistently read twice. Another approach is for the CPU to read the peripheral register only after a status bit indicates the peripheral data is synchronized and stable. These approaches, however, require added CPU software and introduce data latency. Moreover, these techniques can lead to increased system power consumption.